1. Technical Field
The present invention relates to an AD conversion apparatus and a DA conversion apparatus.
2. Related Art
Citation 1 discloses a successive approximation AD converter that uses a PWM circuit and a smoothing circuit. Citations 2 and 3 each disclose an integration AD converter. Citation 4 discloses a sigma-delta AD converter.
Citation 5 discloses a DA converter that charges/discharges a capacitor according to a 1-bit up/down signal. Citation 6 discloses a DA converter that generates in parallel N stages of pulses whose periods each differ by 2N times, and adds these pulses together.    Patent Document 1: Japanese Patent Application Publication No. H07-131353    Patent Document 2: Japanese Patent Application Publication No. 2003-32114    Patent Document 3: Japanese Patent Application Publication No. 2003-143011    Patent Document 4: Japanese Patent Application Publication No. 2000-357968    Patent Document 5: Japanese Patent Application Publication No. 2002-111499    Patent Document 6: Japanese Patent Application Publication No. H06-104763
However, in order to generate a threshold voltage for determining the value of each bit, the successive approximation AD converter must feed back the comparison results and perform a digital computation. In order to count a clock, for example, the integration AD converter must perform a digital adding process. In order to generate a pulse modulation signal, the sigma-delta AD converter must perform a modulation process and an addition/subtraction process according to the comparison results. These AD converters therefore have large digital circuits.
In order to generate the desired voltage, the DA converter of Citation 5 must perform a digital process such as counting the up/down signals. The DA converter of Citation 6 must include N pulse generators.